There are a wide variety of commercially available boats for processing silicon wafers in semiconductor technology. Although such boats are typically for use with silicon wafers or wafers composed of a single semiconductor material, more recent developments in semiconductor technology have been making use of binary materials in which the wafer is composed of more than one element. An example of such a wafer is a silicon-on-sapphire wafer in which one side is composed of silicon whereas the other side is sapphire. When such wafers, as well as silicon wafers, are heated and cooled during a circuit fabrication process, the temperature of one surface increases faster than the other due to difference in thermal properties such as heat absorption, heat conduction, and radiation, or other factors such as in the spacing between adjacent wafers. Thus the thermal expansion of one material is different from the other resulting in a warping of the wafer into a shape much like a potato chip. When the commercially available boats designed for silicon technology are used with such wafers of binary materials, the wafer warpage often exceeds the wafer breaking point and the constraints and pressures imposed on the designs of the prior art processing boats jam the wafers in a given position so that the wafers have a greater tendency to break as they warp during the fabrication process.
The same breakage problem is also present (although to a smaller extent) in silicon wafers due to warpage during processing. In particular during the warping process the effective diameter of the wafer decreases and the wafer settles deeper into the various grooves provided in the prior art boats. As the wafers gradually reach thermal equilibrium the wafers begin to straighten out and as the wafer diameter again increases the wafers jam and break due to the changed position.
The wafer breakage due to the thermal shock and warping is observed in the bulk silicon processing for NMOS, PMOS, CMOS or bipolar circuits. In this case, the front surface of the silicon wafers is polished to a mirror-like surface while the back side is merely lapped. These two surfaces also have different thermal properties and the wafers warp during heating and cooling. Thus, a certain wafer breakage rate exists even in the bulk silicon processing although the breakage rate is lower than the SOS wafers. Magnetic garnet wafers and GaAs wafers have a similar breakage problem as SOS wafers.
Prior to the present invention there has not been a suitable boat for handling and processing wafers, particularly wafers composed of binary material, without an unacceptable breakage percentage.